1. Field of the Invention
The present invention relates to an improvement of a semiconductor device having a trench isolation structure.
2. Background Art
In accordance with miniaturization of a semiconductor element, isolation between elements has also come to be effected on a much more minute scale. A method of defining an isolation region by thermal oxidation of a silicon substrate, what is called Local Oxidation of Silicon (LOCOS), inevitably involves generation of a structural defect called a bird's beak. Thus, the LOCOS method involves a problem of the bird's beak destroying a minute active region sandwiched between the isolation regions. A widely-known approach to solve this problem is to prevent formation of a bird's beak by means of the trench isolation method.
The trench isolation method involves embedding an insulating layer in a trench formed in a silicon substrate. After the insulating layer is embedded in the trench, the film is etched to the vicinity of the primary surface of the silicon substrate. The etched surface is smoothed by means of a widely-used dry etching or chemical-and-mechanical polishing (CMP) method.
As shown in FIG. 23, an active region 11 and an isolation region 21a coexist in a semiconductor substrate 10 of an actual semiconductor device, and an embedded oxide film constituting the isolation region 21a is formed so as to become raised in comparison to the primary surface of the active region 11. Reference numeral 21b designates a bird's beak. In this structure, as in the case of a LOCOS structure, formation of a parasitic MOS can be prevented by raising an isolation oxide film higher than the silicon substrate 10. Further, there can be prevented a reduction in a withstand voltage with respect to a gate, which would otherwise be caused when the edge of an opening of the trench isolation structure becomes steeps.
However, such a conventional semiconductor device suffers the following problems.
FIG. 24 is a cross-sectional view showing the conventional semiconductor device as viewed from the widthwise direction of the gate. As indicated by arrows in the drawing, the effective width of the gate becomes smaller, which in turn diminishes the amount of drain current.
FIG. 25 shows another conventional semiconductor device as viewed from the widthwise direction of the gate. In such an example of the conventional semiconductor device, an n-type layer 16 is formed on, e.g., a p-type layer 15 of the semiconductor substrate 10. In this case, a silicide layer 80 is formed close to the bird's beak 21b, and a junction edge of the n-type layer 16 (which is a reverse conductive layer) beneath the silicide layer 80 comes close to the silicide layer 80. Therefore, a depletion layer is susceptible to becoming closer to the silicide, thereby resulting in a decrease in the withstand voltage of the device.
The conventional trench isolation structure as described above is likely to exhibit a so-called narrow channel effect. Specifically, the threshold voltage of the transistor is likely to increase in association with miniaturization of the semiconductor device and is prone to becoming difficult to control, which in turn results in lack of drain current or makes the semiconductor device inoperable.